RISC-V: The Instruction-Set Alternative

The BeagleV-Fire targets robotics and control applications with a Microchip SoC FPGA.

When Hellen joined Bluespec Inc., she immediately made an impact by playing a lead role in multiple company initiatives that drive adoption and enable innovation with RISC-V. ...

You can view most of the sessions that were presented at the RISC-V Summit.

Open-source RISC-V continues to grab more attention as an option for building customized solutions. What's your stance on the instruction set?

A trio of RISC-V-based microcontroller platforms developed by Synopsys are aimed at MCUs, 32-bit real-time apps, and 64-bit application processors.

How did RISC-V transform from a student project into an architecture that’s being used by organizations, universities, and governments around the world? Let’s dive into the history...

The open-source RISC-V architecture offers new options for those who create microcontroller and microprocessor designs.

By extending the instruction set, a processor can tackle an application more efficiently.

Configurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces.

Building on the CORE-V processor IP, the solution is a full system-on-chip powered by CORE-V and boasts a full suite of peripherals.

The CORE-V Family is a series of RISC-V-based open-source cores that also comes with associated processor subsystem IP, tools, and software.

Part 2 looks at more companies that are on track to adopt the RISC-V architecture for new applications ranging from robotics to home automation.

More companies are on track to adopt the RISC-V architecture for new applications that range from robotics to home automation.

Calista is the CEO of RISC-V International, the organization driving the most prolific open-standard instruction set architecture (ISA) in history. 10,000+ engineers and 300+ ...

With its latest 64-bit RISC-V CPU cores, the P670 and P470, SiFive is putting the focus on compute density.

SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first automotive family...

The open-standard RISC-V instruction set architecture is rewriting the silicon industry's traditional business practices. Let’s explore.

Renesas’ R9A02G020, built around an Andes N22 RISC-V core, takes on motor-control chores.

SiFive's RISC-V CPU cores will sit at the heart of NASA's future spaceflight processor.

The September 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software, and a robust panel discussion.

The CORE-V software developer kit with full-featured Eclipse integrated development environment and an open PCB design was first unveiled at embedded world in Nuremberg in June...

Chief Technology Officer for RISC-V International, Mark Himelstein, introduces new RISC-V standards.

RISC-V offers a level of flexibility to design new processors because the instruction set isn’t defined at the ISA level, but rather is the compilation of the processor and other...

The hybrid RISC-V Week conference will take place May 3-5, 2022.

Editor Bill Wong takes a look at Microchip's FPGA system-on-chip with five RISC-V cores.

To date, the company has raised more than $350 million in funding to build out its core chip design business.

Intel is joining RISC-V International, the body that oversees the open-source instruction set architecture.

Imagination Technologies is returning to the CPU business with a new series of cores based on the RISC-V instruction set.

SiFive CEO Patrick Little discusses the differentiating factors of its new Performance P650 RISC-V core with Editor Bill Wong, as well as its intended applications.

With its P550 performance core and P270 vector core, the company brings more to the high-performance computing table.

This webinar introduces the RISC-V Architecture, providing an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and Interrupts.

Achieve real-time motor control with an FPGA that has its own Ethernet-style connectivity.

Can RISC-V handle GPU chores? Work is underway to make it happen through the creation of a small, area-efficient design with custom programmability and extensibility.

SiFive put one of its RISC-V designs on a Mini-ITX motherboard, which features the company’s FU740 SoC that’s built around four U74 cores and one S7 core in a SMP configuration...

RISC-V is officially a decade old. Here’s a look at what the organization has accomplished and how it’s moving forward with extensions targeting specific computing environments...

Nvidia is using RISC-V for its security processor, and programming is handled via Ada/SPARK.

Microsemi is taking its RISC-V support to the next level with hard-core RISC-V CPUs being integrated with its latest FPGAs.

Despite its rich ecosystem and growing number of real-world implementations, misconceptions about RISC-V are keeping companies around the world from fully realizing its benefits...

In an attempt to achieve the best TFLOPS per watt for machine learning, Esperanto Technologies is adopting RISC-V in its latest processors.

Is real RISC-V going to rescue the Internet of Things? Find out what Technology Editor Bill Wong thinks of SiFive’s latest E310 RISC-V chip.

RISC-V is a scalable open source, RISC instruction set that can be implemented on a range of platforms from custom SoCs to FPGAs.