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The semiconductor industry is entering the age of the chiplet. Today, many of the world’s most advanced chips consist of several smaller silicon dies that are placed on 2.5D packaging or stacked in 3D configurations to mimic a single system-on-chip (SoC). But since it’s such a tight fit inside the package, the challenge is figuring out how to carry the heat out of the stack before it can take a toll on performance.
Melika Roshandell, product marketing director for the Multiphysics System Analysis Group at Cadence, said chip designers face many difficulties when using 3D chip technology. However, “thermal is the number one problem.”
To help figure out where, how, and to what extent everything under the hood of modern chips generates heat, Cadence rolled out Celsius Studio. The solution is designed to accurately model every aspect of the chip, the package, and the system surrounding it—all to identify potential hot spots, determine the impact on performance, and then help engineers figure out ways to reduce heat. The company launched it at DesignCon last month.
Cadence said Celsius Studio uses its multiphysics technology to run electrical and thermal simulations at the same time. Electrothermal simulation, as the company calls it, is a way to accurately predict the impact of heat on the current resistance in chips, packages, and boards, which in turn plays into both performance and reliability. Expanding on its existing Celsius Thermal Solver, it can also evaluate the warping caused by thermal stress.
Importantly, Celsius Studio can analyze the impacts of heat on everything from the chiplets to the packages housing them at each stage in the design process in a methodology called “in-design analysis.” That way, engineers can pinpoint hot spots and sources of thermal stress, which are among the leading failure risks in electronic systems, and then address them before the final design is locked in.
Besides the implications for high-end silicon, Cadence said Celsius Studio also stands out for the ability to analyze cooling technologies on the PCB all the way up to complete systems and physical enclosures.
Heat: A Threat to Everything from Chip to Board to System
Heat ruins everything in electronics. Unless it’s extracted, excess heat can increase the resistance in the power rails inside the chip, the package, and the PCB, resulting in current losses that often sap a system’s performance. Heat can also rear its head in the form of malfunctions or even permanent damage. Since heat presents a problem to every facet of the system—in a transistor, chiplet, chip, package, on a circuit board, and in data centers or other systems—it must be carefully managed.
The temperatures inside modern chips are rising. Today, the most advanced chips are becoming even more power-hungry, burning through huge amounts of dynamic power to handle hefty computations such as AI. As modern chips scale to smaller nodes, leakage current is also becoming a more prominent source of power consumption. Supplying the large currents required by NVIDIA's 1,000-W Blackwell GPU and other server chips is itself a challenge. But dissipating their heat passively (with heatsinks, for instance) or even actively is a daunting task, too.
Reducing the clock frequency of the chip at the heart of the system is one way to prevent overheating, said Roshandell. But she added that this isn’t a palatable tradeoff since it also affects the performance.
Another thermal issue is the tendency of different materials to warp when hot. The chips, packages, and underlying circuit board are all manufactured out of several layers of material, each of which has different thermal expansion properties. When exposed to heat, they start to expand, but they do so at varying rates and to varying extents due to their different internal properties.
If the electronics overheat, they can start warping. That can severely strain the electrical connections in the chip, package, or circuit board, which in turn can fracture and disconnect. The damage is permanent.
These issues are all exacerbated as the semiconductor industry enters the era of 3D heterogeneous integration. Today, many of the latest data center chips are assembled out of several silicon dies that are densely squeezed into interposers or other types of 2.5D packaging or even more advanced 3D stacking technologies. The proximity of the chiplets generates heat. When they’re stacked on top of each other and then on top of the package and the PCB, heat can have trouble escaping, said Roshandell.
Power is also consumed when it comes to ferrying signals between the dies in a package, creating additional heat that must be dissipated before it hurts the performance. Large thermal gradients can persist in the package since it covers a larger area than a traditional SoC.
Better Thermal Management Starts Inside the SoC
Since the heat stemming from the chip itself can negatively impact the thermal situation elsewhere—and vice versa—it’s becoming more important for engineers to co-design every facet of the system together.
By uniting electronic and thermal simulation with electronics cooling and system analysis in a single platform, Cadence said Celsius Studio creates new opportunities for co-designing everything from the chips to the overall system, whether targeted at consumer electronics, defense, aerospace, automotive, or the data center. The company said it bridges the gaps between electronics and mechanical engineers while connecting the worlds of ECAD and MCAD.
Celsius is plugged into the company’s other series of software tools, including Virtuoso for designing analog ICs, Innovus for implementing digital logic, Allegro X for creating the advanced packaging around the IC, Allegro for plotting out the PCB, and AWR Design Environment for RF and microwave ICs.
By being directly integrated with its other tools, Celsius Studio can be used to execute electronic and thermal simulations early and often throughout the design process. It also opens the door for you to predict and improve the performance of the chip by itself as well as all of its applications, including the PCB and the final product, said Cadence.
As it turns out, Celsius Studio can create the thermal profile of the full system from the chip to package to the circuit board and the physical enclosure of the system. These insights can assist engineers with heat-reduction strategies and the optimal placement of everything from heatsinks to thermal vias for heat management on circuit boards and temperature sensors inside the IC package.
These capabilities are bound to be attractive to automakers, hyperscalers, and other large systems companies that are investing more in custom chip designs, especially for AI.
Celsius Studio: Simulations for Heating and Cooling
Cadence said that it incorporated a wide range of improvements under the hood with Celsius Studio.
The offering has more than enough capacity to accurately simulate any object of interest, including chips, packages, boards, heatsinks, fans, and even enclosures in very granular detail, according to the company. It also features “micro-to-macro modeling,” as it can model system components as small as a chip and its power distribution and as large as the chassis where the PCB is placed.
Celsius Studio uses finite element modeling (FEM) to simulate the amount of heat impacting every point of the system as well as the warping of the components, including in situations when the silicon die are stacked on top of each other. It uses another type of simulation called computational fluid dynamics (CFD) to accurately simulate how heat responds to the use of active and passive cooling in a system.
For instance, Roshandell said it can accurately simulate and zoom in on the chiplets in a package, the bumps that supply signals and power, and the interconnects that transfer data between them. She added that Celsius Studio can detect the hot spots within and evaluate why they are there. These insights are useful for improving the arrangement of chiplets for better thermals. You can place temperature sensors in the hotspots to capture and reverse the temperature rise quickly, Roshandell pointed out.
Cadence is also integrating its AI technology into Celsius Studio to guide engineers to the areas of the design that matter most and assist them with the “thermally aware” placement of components in the system, said Roshandell.
Celsius Studio is architected for massively parallel execution, lending itself to fast and frequent simulations.
