Accelerate AI Hardware Design by Magnitudes Using AI-Accelerated Chip Design Methods

September 3, 2024
2:00 PM ET / 1:00 PM CT / 11:00 AM PT / 7:00 PM GMT

Duration: 1 hour
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Summary

AI accelerated design tools can provide order-of-magnitude speedups for a wide range of tasks in chip design, massively reducing both CPU runtime and engineering time for design and verification.

The Challenge

Along with these big AI speedups comes a new challenge – knowing that the AI model is right. Chips need to work, and errors in their design and inaccuracy in verification can lead to expensive yield and respin problems. In order to get big speedups from AI, we are shifting to AI models, which are hard to understand, verify, and trust.

AI adds two main sources of inaccuracy that put AI-accelerated chip designs at risk:

• The AI model can be incorrect altogether
• Even when the model is generally right, the accuracy of the AI answer is an estimate, and it is hard to know how close to correct that estimate is.

The Solution

In this webinar, Jeff Dyck, a leading expert in verifiable AI for chip design, will take us through some of the methods that his team within Siemens EDA uses for automatically proving correctness and accuracy of AI models. We will review different classes of accuracy and verifiability in chip design algorithms, discuss techniques for automatically verifying AI models on the fly, and will dive into a theoretical explanation and demo of one of the world’s most proven AI-accelerated chip design methods – Solido High-Sigma Verifier.